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EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
15 years 10 months ago
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng
ASPDAC
2007
ACM
92views Hardware» more  ASPDAC 2007»
15 years 10 months ago
New Block-Based Statistical Timing Analysis Approaches Without Moment Matching
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Ma...
Ruiming Chen, Hai Zhou
DEBS
2007
ACM
15 years 10 months ago
Adapting publish-subscribe routing to traffic demands
Most of currently available content-based publish-subscribe systems that were designed to operate in large scale, wired scenarios, build their routing infrastructure as a set of b...
Matteo Migliavacca, Gianpaolo Cugola
APSCC
2006
IEEE
15 years 10 months ago
GridPPI: A Lightweight Grid-Enabled Parallel Programming Framework
Parallel application development for Grids can from tools that abstract the underlying Grid middleware, hide the critical aspects of heterogeneous resources and provide utilities ...
Sikan Chen, Minglu Li, Feng He
ACSC
2001
IEEE
15 years 10 months ago
TRAM: A Tool for Requirements and Architecture Management
Management of system requirements and system architectures is part of any software engineering project. But it is usually very tedious and error prone. In particular, managing the...
Jun Han