Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
The IEEE 1149.6 standard was approved in March of 2003. The standard extends the capability of the IEEE 1149.1 standard to include AC-coupled and/or differential nets. These nets ...
Bill Eklow, Carl Barnhart, Mike Ricchetti, Terry B...
Avoiding architectural erosion helps extend the lifetime of an evolving software system. Erosion can be reduced by ensuring that (i) developers share a good understanding of a sys...
Ciaran O'Reilly, Philip J. Morrow, David W. Bustar...
— Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip. Sharing IP blocks in such a competitive market poses significant h...
The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extra...
Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Pa...