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ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
16 years 3 months ago
Algorithms for MIS vector generation and pruning
Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run...
Kenneth S. Stevens, Florentin Dartu
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
16 years 3 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
ICCAD
2001
IEEE
180views Hardware» more  ICCAD 2001»
16 years 3 months ago
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits
This paper attempts to determine the capabilities of existing Redundancy Addition and Removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we ...
Enrique San Millán, Luis Entrena, Jos&eacut...
CVPR
2010
IEEE
16 years 3 months ago
A Hough Transform-Based Voting Framework for Action Recognition
We present a method to classify and localize human actions in video using a Hough transform voting framework. Random trees are trained to learn a mapping between densely-sampled f...
Angela Yao, Juergen Gall, Luc Van Gool
CVPR
2010
IEEE
16 years 2 months ago
Detecting and Parsing Architecture at City Scale from Range Data
We present a method for detecting and parsing buildings from unorganized 3D point clouds into a compact, hierarchical representation that is useful for high-level tasks. The input...
Alexander Toshev, Philippos Mordohai, Ben Taskar