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» Cost-Sharing Mechanisms for Network Design
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ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
16 years 3 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...
NOCS
2008
IEEE
16 years 21 days ago
Reducing the Interconnection Network Cost of Chip Multiprocessors
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
Pablo Abad, Valentin Puente, José-Án...
IPPS
2006
IEEE
16 years 10 days ago
Dynamic power saving in fat-tree interconnection networks using on/off links
Current trends in high-performance parallel computers show that fat-tree interconnection networks are one of the most popular topologies. The particular characteristics of this to...
Marina Alonso, Salvador Coll, Juan Miguel Mart&iac...
ICC
2000
IEEE
123views Communications» more  ICC 2000»
15 years 10 months ago
A Per-Flow Based Node Architecture for Integrated Services Packet Networks
As the Internet transforms from the traditional best-effort service network into QoS-capable multi-service network, it is essential to have new architectural design and appropriate...
Dapeng Wu, Yiwei Thomas Hou, Takeo Hamada, Zhi-Li ...
DSD
2006
IEEE
120views Hardware» more  DSD 2006»
16 years 11 days ago
Adaptive Power Management for the On-Chip Communication Network
— An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this regi...
Guang Liang, Axel Jantsch