548 search results - page 25 / 110 » Core-Selectability in Chip Multiprocessors |
138
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DATE
2004
IEEE
15 years 9 months ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
144
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DATE
2005
IEEE
15 years 11 months ago
2005
IEEE
In this paper is proposed a technique to integrate and simulate a dynamic memory in a multiprocessor framework based on C/C++/SystemC. Using host machine’s memory management cap...
152
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PPOPP
2009
ACM
16 years 6 months ago
2009
ACM
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
156
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HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
162
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HIPEAC
2010
Springer
16 years 3 months ago
2010
Springer
As CMOS feature sizes venture deep into the nanometer regime, wearout mechanisms including negative-bias temperature instability and timedependent dielectric breakdown can severely...