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TCAD
2010
154views more  TCAD 2010»
15 years 1 months ago
Automated Design Debugging With Maximum Satisfiability
As contemporary VLSI designs grow in complexity, design debugging has rapidly established itself as one of the largest bottlenecks in the design cycle today. Automated debug soluti...
Yibin Chen, Sean Safarpour, João Marques-Si...
DAC
2004
ACM
16 years 7 months ago
A SAT-based algorithm for reparameterization in symbolic simulation
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening
WSDM
2009
ACM
161views Data Mining» more  WSDM 2009»
16 years 1 months ago
Predicting the readability of short web summaries
Readability is a crucial presentation attribute that web summarization algorithms consider while generating a querybaised web summary. Readability quality also forms an important ...
Tapas Kanungo, David Orr
EMSOFT
2009
Springer
16 years 1 months ago
Cache-aware scheduling and analysis for multicores
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms...
Nan Guan, Martin Stigge, Wang Yi, Ge Yu
DSN
2007
IEEE
16 years 28 days ago
BlackJack: Hard Error Detection with Redundant Threads on SMT
Testing is a difficult process that becomes more difficult with scaling. With smaller and faster devices, tolerance for errors shrinks and devices may act correctly under certain ...
Ethan Schuchman, T. N. Vijaykumar