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ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 11 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
ETS
2010
IEEE
174views Hardware» more  ETS 2010»
15 years 7 months ago
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
EOR
2006
80views more  EOR 2006»
15 years 6 months ago
Vehicle routing and crew scheduling for metropolitan mail distribution at Australia Post
This paper presents a new multi-depot combined vehicle and crew scheduling algorithm, and uses it, in conjunction with a heuristic vehicle routing algorithm, to solve the intra-ci...
B. L. Hollis, M. A. Forbes, B. E. Douglas
ICCAD
2009
IEEE
161views Hardware» more  ICCAD 2009»
15 years 4 months ago
The epsilon-approximation to discrete VT assignment for leakage power minimization
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
Yujia Feng, Shiyan Hu
CORR
2010
Springer
160views Education» more  CORR 2010»
15 years 3 months ago
Routing with Mutual Information Accumulation in Wireless Networks
We investigate optimal routing and scheduling strategies for multi-hop wireless networks with rateless codes. Rateless codes allow each node of the network to accumulate mutual in...
Rahul Urgaonkar, Michael J. Neely