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DAC
1999
ACM
15 years 10 months ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
SIES
2008
IEEE
16 years 8 days ago
Performance evaluation of a java chip-multiprocessor
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
Christof Pitter, Martin Schoeberl
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
15 years 11 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...
ISSA
2004
15 years 7 months ago
High Data Rate 8-Bit Crypto Processor
This paper describes a high data rate 8-bit Crypto Processor based on Advanced Encryption Standard (Rijndael algorithm). Though the algorithm requires 32-bit wide data path but ou...
Sheikh Muhammad Farhan
ASPLOS
2008
ACM
15 years 8 months ago
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs
Extracting high-performance from the emerging Chip Multiprocessors (CMPs) requires that the application be divided into multiple threads. Each thread executes on a separate core t...
M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Pa...