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ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
16 years 2 days ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
CODES
2003
IEEE
15 years 11 months ago
Synthesis of real-time embedded software with local and global deadlines
Current methods cannot synthesize real-time embedded software applications when the global deadline of a task is shorter than the total of all local deadlines along a critical pat...
Pao-Ann Hsiung, Cheng-Yi Lin
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 10 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
RTCSA
1998
IEEE
15 years 10 months ago
Protocol Synthesis from Context-Free Processes Using Event Structures
In this paper, we propose a protocol synthesis method based on a partial order model (called event structures) for the class of context-free processes. First, we assign a unique n...
Akio Nakata, Teruo Higashino, Kenichi Taniguchi
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 10 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...