A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapat...
In this paper we brie
y describe a set of designs that can serve as examples for High Level Synthesis (HLS) systems. The designs vary in complexity from simple behavioral nite st...
In this paper, two anticontrol algorithms for synthesis of discrete chaos are introduced. In these algorithms, the control parameter of a discrete dynamical system is switched, ei...
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
In this paper, the problem of synthesizing controllers that ensures non interference for multilevel security dense timed discrete event systems modeled by an extension of Timed Au...