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DAC
2006
ACM
16 years 7 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
ESORICS
2009
Springer
16 years 7 months ago
Type-Based Analysis of PIN Processing APIs
We examine some known attacks on the PIN verification framework, based on weaknesses of the security API for the tamperresistant Hardware Security Modules used in the network. We s...
Matteo Centenaro, Riccardo Focardi, Flaminia L. Lu...
ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
16 years 3 months ago
An Efficient VLIW DSP Architecture for Baseband Processing
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-...
CANDC
2009
ACM
16 years 1 months ago
A sub-symbolic model of the cognitive processes of re-representation and insight
We present a sub-symbolic computational model for effecting knowledge re-representation and insight. Given a set of data, manifold learning is used to automatically organize the d...
Dan Ventura
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
15 years 11 months ago
Parallel Processing Architectures for Reconfigurable Systems
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
Kees A. Vissers