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STTT
2008
117views more  STTT 2008»
15 years 7 months ago
An approach to quality engineering of TTCN-3 test specifications
Abstract Experience with the development and maintenance of large test suites specified using the Testing and Test Control Notation (TTCN-3) has shown that it is difficult to const...
Helmut Neukirchen, Benjamin Zeiss, Jens Grabowski
TVLSI
2008
116views more  TVLSI 2008»
15 years 7 months ago
Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs
Abstract--In this paper, we introduce a novel substrate noise estimation technique during early floorplanning for mixed signal system-on-chip (SOC), based on block preference direc...
Minsik Cho, David Z. Pan
JCT
1998
57views more  JCT 1998»
15 years 7 months ago
The Veronese Surface in PG(5, 3) and Witt's 5-(12, 6, 1) Design
A conic of the Veronese surface in PG(5, 3) is a quadrangle. If one such quadrangle is replaced with its diagonal triangle, then one obtains a point model K for Witt’s 5–(12, ...
Hans Havlicek
NPL
1998
175views more  NPL 1998»
15 years 7 months ago
Prediction of Chaotic Time-Series with a Resource-Allocating RBF Network
Abstract. One of the main problems associated with arti cial neural networks online learning methods is the estimation of model order. In this paper, we report about a new approach...
Roman Rosipal, Milos Koska, Igor Farkas
TCAD
2002
128views more  TCAD 2002»
15 years 7 months ago
Preferred direction Steiner trees
Interconnect optimization for VLSI circuits has received wide attention. To model routing surfaces, multiple circuit layers are freabstracted as a single rectilinear plane, ignori...
Mehmet Can Yildiz, Patrick H. Madden