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» Constraints as a design pattern
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GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
16 years 1 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
184
Voted
DAC
2006
ACM
16 years 8 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
DATE
2010
IEEE
118views Hardware» more  DATE 2010»
15 years 5 months ago
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
Minje Jun, Sungroh Yoon, Eui-Young Chung
170
Voted
COMPSAC
2002
IEEE
16 years 7 days ago
Software Maintainability Improvement: Integrating Standards and Models
Software standards are highly recommended because they promise faster and more efficient ways for software development with proven techniques and standard notations. Designers who...
William C. Chu, Chih-Wei Lu, Chih-Hung Chang, Yeh-...
161
Voted
OOPSLA
1995
Springer
15 years 10 months ago
How and Why to Encapsulate Class Trees
eusable framework, pattern or module interface usually is represented by abstract They form an abstract design and leave the implementation to concrete subclasses. ract design is ...
Dirk Riehle