Sciweavers

7557 search results - page 530 / 1512
» Constraints as a design pattern
Sort
View
ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
16 years 4 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
16 years 1 months ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin
ICCAD
1994
IEEE
92views Hardware» more  ICCAD 1994»
15 years 11 months ago
Synthesis of manufacturable analog circuits
? We describe a synthesis system that takes operating range constraints and inter- and intra- circuit parametric manufacturing variations into account while designing a sized and b...
Tamal Mukherjee, L. Richard Carley, Rob A. Rutenba...
FPL
2006
Springer
85views Hardware» more  FPL 2006»
15 years 11 months ago
High-Performance and Parameterized Matrix Factorization on FPGAs
FPGAs have become an attractive choice for scientific computing. In this paper, we propose a high performance design for LU decomposition, a key kernel in many scientific and engi...
Ling Zhuo, Viktor K. Prasanna
CASES
2008
ACM
15 years 9 months ago
Exploring and predicting the architecture/optimising compiler co-design space
Embedded processor performance is dependent on both the underlying architecture and the compiler optimisations applied. However, designing both simultaneously is extremely difficu...
Christophe Dubach, Timothy M. Jones, Michael F. P....