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CHES
2003
Springer
146views Cryptology» more  CHES 2003»
15 years 10 months ago
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs
Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentifu...
François-Xavier Standaert, Gaël Rouvro...
202
Voted
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
15 years 9 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
WCNC
2010
IEEE
15 years 5 months ago
Robust Relay Precoder Design for MIMO-Relay Networks
Abstract—In this paper, we consider a robust design of MIMOrelay precoder and receive filter for the destination nodes in a non-regenerative multiple-input multiple-output (MIMO...
P. Ubaidulla, Ananthanarayanan Chockalingam
CDC
2010
IEEE
122views Control Systems» more  CDC 2010»
15 years 2 months ago
Closed-loop optimal experiment design: The partial correlation approach
Abstract-- We consider optimal experiment design for parametric prediction error system identification of linear timeinvariant systems in closed loop. The optimisation is performed...
Roland Hildebrand, Michel Gevers, Gabriel Solari
TII
2011
206views Education» more  TII 2011»
15 years 2 months ago
Timing-Failure Risk Assessment of UML Design Using Time Petri Net Bound Techniques
Abstract—Software systems that do not meet their timing constraints can cause risks. In this work, we propose a comprehensive method for assessing the risk of timing failure by e...
Simona Bernardi, Javier Campos, José Merseg...