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» Constraints as a design pattern
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ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
15 years 11 months ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
15 years 11 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
CODES
2001
IEEE
15 years 10 months ago
A design framework to efficiently explore energy-delay tradeoffs
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
William Fornaciari, Donatella Sciuto, Cristina Sil...
CODES
2008
IEEE
15 years 9 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
DSD
2008
IEEE
139views Hardware» more  DSD 2008»
15 years 9 months ago
Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration
Platform-based design represents the most widely used approach to design System-On-Chip (SOC) applications. In this context, the Design Space Exploration (DSE) phase consists of o...
Gianluca Palermo, Cristina Silvano, Vittorio Zacca...