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ISPD
1998
ACM
111views Hardware» more  ISPD 1998»
15 years 10 months ago
A pattern matching algorithm for verification and analysis of very large IC layouts
We propose a simple, isometry invariant pattern matching algorithm for an effective data reduction useful in layout-related data processing of very complex IC designs. The repeata...
Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojw...
DSD
2010
IEEE
171views Hardware» more  DSD 2010»
15 years 5 months ago
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
Jiri Balcarek, Petr Fiser, Jan Schmidt
FASE
2001
Springer
15 years 11 months ago
A Hoare Calculus for Verifying Java Realizations of OCL-Constrained Design Models
Abstract. The Object Constraint Language OCL offers a formal notation for constraining the modelling elements occurring in UML diagrams. In this paper we apply OCL for developing ...
Bernhard Reus, Martin Wirsing, Rolf Hennicker
RTCSA
2008
IEEE
16 years 27 days ago
A Framework for Designing Embedded Real-Time Controllers
Control systems are typically designed assuming an ideal behavior of the computing infrastructure where controllers execute. In practice, however, in highly loaded computing syste...
Yifan Wu, Enrico Bini, Giorgio C. Buttazzo