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ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
16 years 1 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
SENSYS
2009
ACM
16 years 1 months ago
Mercury: a wearable sensor network platform for high-fidelity motion analysis
This paper describes Mercury, a wearable, wireless sensor platform for motion analysis of patients being treated for neuromotor disorders, such as Parkinson’s Disease, epilepsy,...
Konrad Lorincz, Bor-rong Chen, Geoffrey Werner Cha...
MICRO
2009
IEEE
148views Hardware» more  MICRO 2009»
16 years 1 months ago
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmab...
Sangyeun Cho, Hyunjin Lee
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
16 years 20 days ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
CODES
2006
IEEE
16 years 17 days ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
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