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DATE
2000
IEEE
136views Hardware» more  DATE 2000»
15 years 11 months ago
On Applying Incremental Satisfiability to Delay Fault Testing
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...
DATE
2000
IEEE
108views Hardware» more  DATE 2000»
15 years 11 months ago
A 50 Mbit/s Iterative Turbo-Decoder
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive codin...
F. Viglione, Guido Masera, Gianluca Piccinini, Mas...
IPPS
2000
IEEE
15 years 11 months ago
Real-Time Transaction Processing Using Two-Stage Validation in Broadcast Disks
Conventional concurrency control protocols are inapplicable in mobile computing environments due to a number of constraints of wireless communications. In this paper, we design a p...
Kwok-Wa Lam, Victor C. S. Lee, Sang Hyuk Son
IPPS
2000
IEEE
15 years 11 months ago
Switch Scheduling in the Multimedia Router (MMR)
The primary goal of the Multimedia Router (MMR) project is the design and implementation of a router optimized for multimedia applications. The router is targeted for use in clust...
Damon S. Love, Sudhakar Yalamanchili, José ...
ASPDAC
2000
ACM
159views Hardware» more  ASPDAC 2000»
15 years 11 months ago
Analytical minimization of half-perimeter wirelength
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
Andrew A. Kennings, Igor L. Markov
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