7557 search results - page 1249 / 1512 » Constraints as a design pattern |
168
click to vote
ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
158
click to vote
ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
157
click to vote
ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
213
click to vote
ISQED
2010
IEEE
16 years 1 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
168
click to vote
AOSD
2010
ACM
16 years 1 months ago
2010
ACM
Many software security policies can be encoded as aspects that identify and guard security-relevant program operations. Bugs in these aspectually-implemented security policies oft...