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196
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ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
16 years 3 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
165
Voted
ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
16 years 3 months ago
A Two-Layer Bus Routing Algorithm for High-Speed Boards
The increasing clock frequencies in high-end industrial circuits bring new routing challenges that can not be handled by traditional algorithms. An important design automation pro...
Muhammet Mustafa Ozdal, Martin D. F. Wong
151
Voted
ICCAD
2002
IEEE
109views Hardware» more  ICCAD 2002»
16 years 3 months ago
Methods for true power minimization
This paper presents methods for efficient power minimization at circuit and micro-architectural levels. The potential energy savings are strongly related to the energy profile of ...
Robert W. Brodersen, Mark Horowitz, Dejan Markovic...
194
Voted
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
16 years 3 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
AOSD
2010
ACM
16 years 1 months ago
Disambiguating aspect-oriented security policies
Many software security policies can be encoded as aspects that identify and guard security-relevant program operations. Bugs in these aspectually-implemented security policies oft...
Micah Jones, Kevin W. Hamlen