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ICPP
2009
IEEE
16 years 1 months ago
Accelerating Checkpoint Operation by Node-Level Write Aggregation on Multicore Systems
—Clusters and applications continue to grow in size while their mean time between failure (MTBF) is getting smaller. Checkpoint/Restart is becoming increasingly important for lar...
Xiangyong Ouyang, Karthik Gopalakrishnan, Dhabales...
ISCA
2009
IEEE
239views Hardware» more  ISCA 2009»
16 years 1 months ago
Scalable high performance main memory system using phase-change memory technology
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Ju...
MICRO
2009
IEEE
148views Hardware» more  MICRO 2009»
16 years 1 months ago
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmab...
Sangyeun Cho, Hyunjin Lee
EMSOFT
2009
Springer
16 years 28 days ago
Cache-aware scheduling and analysis for multicores
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms...
Nan Guan, Martin Stigge, Wang Yi, Ge Yu
MHCI
2009
Springer
16 years 27 days ago
User evaluation of lightweight user authentication with a single tri-axis accelerometer
We report a series of user studies that evaluate the feasibility and usability of light-weight user authentication with a single tri-axis accelerometer. We base our investigation ...
Jiayang Liu, Lin Zhong, Jehan Wickramasuriya, Venu...
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