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DAC
1996
ACM
15 years 10 months ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
IJPP
2011
115views more  IJPP 2011»
14 years 9 months ago
Milepost GCC: Machine Learning Enabled Self-tuning Compiler
Tuning compiler optimizations for rapidly evolving hardware makes porting and extending an optimizing compiler for each new platform extremely challenging. Iterative optimization i...
Grigori Fursin, Yuriy Kashnikov, Abdul Wahid Memon...
LCPC
2005
Springer
15 years 11 months ago
Compiler Control Power Saving Scheme for Multi Core Processors
With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten developmen...
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroak...
PPAM
2005
Springer
15 years 11 months ago
SILC: A Flexible and Environment-Independent Interface for Matrix Computation Libraries
We propose a new framework, named Simple Interface for Library Collections (SILC), that gives users access to matrix computation libraries in a flexible and environment-independen...
Tamito Kajiyama, Akira Nukada, Hidehiko Hasegawa, ...
AAAI
2010
15 years 7 months ago
A First Practical Algorithm for High Levels of Relational Consistency
Consistency properties and algorithms for achieving them are at the heart of the success of Constraint Programming. In this paper, we study the relational consistency property R(,...
Shant Karakashian, Robert J. Woodward, Christopher...