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DAC
2007
ACM
16 years 7 months ago
Gate Sizing For Cell Library-Based Designs
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shif...
Shiyan Hu, Mahesh Ketkar, Jiang Hu
ISCAS
2008
IEEE
133views Hardware» more  ISCAS 2008»
16 years 21 days ago
A hybrid self-testing methodology of processor cores
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
DSN
2007
IEEE
15 years 10 months ago
Augmenting Branch Predictor to Secure Program Execution
Although there are various ways to exploit software vulnerabilities for malicious attacks, the attacks always result in unexpected behavior in program execution, deviating from wh...
Yixin Shi, Gyungho Lee
DAC
2003
ACM
16 years 7 months ago
A scalable software-based self-test methodology for programmable processors
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit D...
CHI
2002
ACM
16 years 6 months ago
Direct manipulation interface for architectural design tools
The early architectural design stage is a typical example where traditional design tools such as sketching on paper still dominate over computer-assisted tools. Augmented reality ...
Dzmitry Aliakseyeu