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DATE
2006
IEEE
124views Hardware» more  DATE 2006»
16 years 11 days ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
FPL
2005
Springer
98views Hardware» more  FPL 2005»
15 years 11 months ago
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be...
Gareth W. Morris, George A. Constantinides, Peter ...
DAC
1997
ACM
15 years 10 months ago
More Practical Bounded-Skew Clock Routing
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
Andrew B. Kahng, Chung-Wen Albert Tsao
CF
2005
ACM
15 years 8 months ago
Dynamic loop pipelining in data-driven architectures
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
João M. P. Cardoso
CP
2010
Springer
15 years 4 months ago
A Box-Consistency Contractor Based on Extremal Functions
Abstract. Interval-based methods can approximate all the real solutions of a system of equations and inequalities. The Box interval constraint propagation algorithm enforces Box co...
Gilles Trombettoni, Yves Papegay, Gilles Chabert, ...