Abstract— We analyze the performance of likelihoodbased approaches used to reconstruct phylogenetic trees. Unlike other techniques such as Neighbor-Joining (NJ) and Maximum Parsi...
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
Arbitrary faults of a single node in a time-triggered architecture (TTA) bus topology system may cause error propagation to correct nodes and may lead to inconsistent system state...
This work discusses the use of an Evolvable Hardware (EHW) platform in the synthesis of analog electronic circuits for Fuzzy Logic Controllers. A Fuzzy Logic Controller (FLC) is d...
This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit Digital to Analog Converter (DAC) using the JPL stand-alo...
Ricardo Salem Zebulum, Didier Keymeulen, Vu Duong,...