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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
15 years 11 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
EMNETS
2007
15 years 10 months ago
SeeDTV: deployment-time validation for wireless sensor networks
Deployment of a wireless sensor network (WSN) system is a critical step because theoretical models and assumptions often differ from real environmental characteristics and perform...
H. Liu, Leo Selavo, John A. Stankovic
AINA
2003
IEEE
15 years 10 months ago
Formal Verification of Condition Data Flow Diagrams for Assurance of Correct Network Protocols
Condition Data Flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon Data Flow Diagrams, Petri Nets, and pre-post notation. They are used in th...
Shaoying Liu
VISUALIZATION
1995
IEEE
15 years 10 months ago
Virtual GIS: A Real-Time 3D Geographic Information System
Advances in computer graphics hardware and algorithms, visualization, and interactive techniques for analysis offer the components for a highly integrated, efficient real-time 3D ...
David Koller, Peter Lindstrom, William Ribarsky, L...
SIGGRAPH
1991
ACM
15 years 10 months ago
Design and simulation of opera lighting and projection effects
A major problem challenging opera designers is the inability to coordinate lighting, projection systems, and set designs in the preliminary planning phase. New computer graphics t...
Julie Dorsey, François X. Sillion, Donald P...