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ACMMSP
2005
ACM
115views Hardware» more  ACMMSP 2005»
16 years 10 days ago
Performance characteristics of MAUI: an intelligent memory system architecture
Combining ideas from several previous proposals, such as Active Pages, DIVA, and ULMT, we present the Memory Arithmetic Unit and Interface (MAUI) architecture. Because the “inte...
Justin Teller, Charles B. Silio Jr., Bruce L. Jaco...
178
Voted
ACMSE
2005
ACM
16 years 10 days ago
Exploring communication overheads and locking policies in a peer-to-peer synchronous collaborative editing system
In this paper, we describe recent work in developing a peer-topeer collaborative environment. The study examines various locking mechanisms/policies by adjusting the granularity o...
Jon A. Preston, Sushil K. Prasad
ASPDAC
2005
ACM
140views Hardware» more  ASPDAC 2005»
16 years 10 days ago
A multi-level transmission line network approach for multi-giga hertz clock distribution
-In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and m...
Hongyu Chen, Chung-Kuan Cheng
ASPDAC
2005
ACM
86views Hardware» more  ASPDAC 2005»
16 years 10 days ago
Thermal-driven multilevel routing for 3-D ICs
3-D IC has a great potential for improving circuit performance and degree of integration. It is also an attractive platform for system-on-chip or system-in-package solutions. A cr...
Jason Cong, Yan Zhang
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
16 years 10 days ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
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