2186 search results - page 172 / 438 » Considering an Organization's Memory |
172
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CASES
2009
ACM
15 years 10 months ago
2009
ACM
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
221
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FPGA
2010
ACM
15 years 6 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
222
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ASPLOS
2011
ACM
14 years 10 months ago
2011
ACM
Cloud services accessed through mobile devices suffer from high network access latencies and are constrained by energy budgets dictated by the devices’ batteries. Radio and batt...
165
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ISPAN
2008
IEEE
16 years 1 months ago
2008
IEEE
Data prefetching has been considered an effective way to mask data access latency caused by cache misses and to bridge the performance gap between processor and memory. With hardw...
162
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SIGMETRICS
1998
ACM
15 years 10 months ago
1998
ACM
While much work has been devoted to the study of cache behavior during the execution of codes with regular access patterns, little attention has been paid to irregular codes. An i...