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ICCAD
2007
IEEE
116views Hardware» more  ICCAD 2007»
16 years 3 months ago
Device and architecture concurrent optimization for FPGA transient soft error rate
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
Yan Lin, Lei He
CLUSTER
2007
IEEE
16 years 28 days ago
Non-collective parallel I/O for global address space programming models
— Achieving high performance for out-of-core applications typically involves explicit management of the movement of data between the disk and the physical memory. We are developi...
Sriram Krishnamoorthy, Juan Piernas, Vinod Tippara...
DATE
2003
IEEE
97views Hardware» more  DATE 2003»
15 years 12 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
ICPPW
2003
IEEE
15 years 12 months ago
A Dynamic Load Balancing Scheme for I/O-Intensive Applications in Distributed Systems
In this paper, a new I/O-aware load-balancing scheme is presented to improve overall performance of a distributed system with a general and practical workload including I/O activi...
Xiao Qin, Hong Jiang, Yifeng Zhu, David R. Swanson
SCCC
2002
IEEE
15 years 11 months ago
Improved Antidictionary Based Compression
The compression of binary texts using antidictionaries is a novel technique based on the fact that some substrings (called “antifactors”) never appear in the text. Let × be a...
Maxime Crochemore, Gonzalo Navarro