Sciweavers

1798 search results - page 300 / 360
» Considerations for the design of exergames
Sort
View
DATE
2005
IEEE
113views Hardware» more  DATE 2005»
15 years 11 months ago
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda...
DSRT
2005
IEEE
15 years 11 months ago
Modeling Real-Time Distributed Simulation Message Flow in an Open Network
Understanding the characteristics of information flow in large scale real-time distributed virtual simulations (RT-DVS) is important for the development of network services that a...
Dennis M. Moen, J. Mark Pullen
AOSD
2005
ACM
15 years 11 months ago
An expressive aspect language for system applications with Arachne
C applications, in particular those using operating system level services, frequently comprise multiple crosscutting concerns: network protocols and security are typical examples ...
Rémi Douence, Thomas Fritz, Nicolas Loriant...
PPOPP
2005
ACM
15 years 11 months ago
Exposing speculative thread parallelism in SPEC2000
As increasing the performance of single-threaded processors becomes increasingly difficult, consumer desktop processors are moving toward multi-core designs. One way to enhance th...
Manohar K. Prabhu, Kunle Olukotun
SIGCOMM
2005
ACM
15 years 11 months ago
Fast hash table lookup using extended bloom filter: an aid to network processing
Hash table is used as one of the fundamental modules in several network processing algorithms and applications such as route lookup, packet classification, per-flow state manage...
Haoyu Song, Sarang Dharmapurikar, Jonathan S. Turn...