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GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
14 years 10 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
SIGSOFT
1994
ACM
15 years 10 months ago
Data Flow Analysis for Verifying Properties of Concurrent Programs
In this paper we present an approach, based on data ow analysis, that can provide cost-e ective analysis of concurrent programs with respect to explicitly stated correctness prope...
Matthew B. Dwyer, Lori A. Clarke
ISRR
2001
Springer
105views Robotics» more  ISRR 2001»
15 years 10 months ago
Towards Robust Data Association and Feature Modeling for Concurrent Mapping and Localization
One of the most challenging aspects of concurrent mapping and localization (CML) is the problem of data association. Because of uncertainty in the origins of sensor measurements, i...
John J. Leonard, Paul M. Newman, Richard J. Rikosk...
IPPS
2003
IEEE
15 years 11 months ago
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
Ying Chen, Resit Sendag, David J. Lilja
SIGSOFT
2009
ACM
16 years 7 months ago
Static data race detection for concurrent programs with asynchronous calls
A large number of industrial concurrent programs are being designed based on a model which combines threads with event-based communication. These programs consist of several threa...
Vineet Kahlon, Nishant Sinha, Erik Kruus, Yun Zhan...