This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
In this paper we present an approach, based on data ow analysis, that can provide cost-e ective analysis of concurrent programs with respect to explicitly stated correctness prope...
One of the most challenging aspects of concurrent mapping and localization (CML) is the problem of data association. Because of uncertainty in the origins of sensor measurements, i...
John J. Leonard, Paul M. Newman, Richard J. Rikosk...
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
A large number of industrial concurrent programs are being designed based on a model which combines threads with event-based communication. These programs consist of several threa...
Vineet Kahlon, Nishant Sinha, Erik Kruus, Yun Zhan...