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CJ
2006
84views more  CJ 2006»
15 years 6 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
SIAMCOMP
1998
117views more  SIAMCOMP 1998»
15 years 6 months ago
The Queue-Read Queue-Write PRAM Model: Accounting for Contention in Parallel Algorithms
This paper introduces the queue-read, queue-write (qrqw) parallel random access machine (pram) model, which permits concurrent reading and writing to shared memory locations, but ...
Phillip B. Gibbons, Yossi Matias, Vijaya Ramachand...
CLUSTER
2011
IEEE
14 years 6 months ago
Performance Characterization and Optimization of Atomic Operations on AMD GPUs
—Atomic operations are important building blocks in supporting general-purpose computing on graphics processing units (GPUs). For instance, they can be used to coordinate executi...
Marwa Elteir, Heshan Lin, Wu-chun Feng
EWSN
2004
Springer
16 years 6 months ago
Tracking Real-World Phenomena with Smart Dust
Abstract. So-called "Smart Dust" is envisioned to combine sensing, computing, and wireless communication capabilities in an autonomous, dust-grain-sized device. Dense net...
Kay Römer
ICASSP
2009
IEEE
16 years 1 months ago
An EM algorithm for SCFG in formal syntax-based translation
In this paper, we investigate the use of bilingual parsing on parallel corpora to better estimate the rule parameters in a formal syntax-based machine translation system, which ar...
Songfang Huang, Bowen Zhou