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ISCA
1999
IEEE
96views Hardware» more  ISCA 1999»
15 years 10 months ago
PipeRench: A Coprocessor for Streaming multimedia Acceleration
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes ...
Seth Copen Goldstein, Herman Schmit, Matthew Moe, ...
MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
15 years 10 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
RTSS
1999
IEEE
15 years 10 months ago
Design and Evaluation of a Feedback Control EDF Scheduling Algorithm
Despite the significant body of results in real-time scheduling, many real world problems are not easily supported. While algorithms such as Earliest Deadline First, Rate Monotoni...
Chenyang Lu, John A. Stankovic, Gang Tao, Sang Hyu...
DATE
1998
IEEE
92views Hardware» more  DATE 1998»
15 years 10 months ago
Multiple Behavior Module Synthesis Based on Selective Groupings
In this paper, we present an approach to synthesize multiple behavior modules. Given n DFGs to be implemented, the previous methods scheduled each of them sequentially, and implem...
Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwa...
ICS
1999
Tsinghua U.
15 years 10 months ago
Low-level router design and its impact on supercomputer system performance
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
Valentin Puente, José A. Gregorio, Cruz Izu...