5180 search results - page 746 / 1036 » Concurrency, Time, and Constraints |
301
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ASPLOS
2009
ACM
16 years 7 months ago
2009
ACM
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
293
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ASPLOS
2009
ACM
16 years 7 months ago
2009
ACM
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
278
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ASPLOS
2009
ACM
16 years 7 months ago
2009
ACM
While deterministic replay of parallel programs is a powerful technique, current proposals have shortcomings. Specifically, software-based replay systems have high overheads on mu...
159
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SPAA
2009
ACM
16 years 7 months ago
2009
ACM
Work stealing is a popular method of scheduling fine-grained parallel tasks. The performance of work stealing has been extensively studied, both theoretically and empirically, but...
233
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HPCA
2005
IEEE
16 years 7 months ago
2005
IEEE
Hardware transactional memory should support unbounded transactions: transactions of arbitrary size and duration. We describe a hardware implementation of unbounded transactional ...