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CORR
2006
Springer
116views Education» more  CORR 2006»
15 years 6 months ago
Memory Aware High-Level Synthesis for Embedded Systems
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
Gwenolé Corre, Eric Senn, Nathalie Julien, ...
CORR
2010
Springer
136views Education» more  CORR 2010»
15 years 4 months ago
Schaefer's theorem for graphs
Schaefer's theorem is a complexity classification result for so-called Boolean constraint satisfaction problems: it states that every Boolean constraint satisfaction problem ...
Manuel Bodirsky, Michael Pinsker
ISORC
2003
IEEE
16 years 3 days ago
Enhancing Time Triggered Scheduling with Value Based Overload Handling and Task Migration
Time triggered methods provide deterministic behaviour suitable for critical real-time systems. They perform less favourably, however, if the arrival times of some activities are ...
Jan Carlson, Tomas Lennvall, Gerhard Fohler
ASPDAC
2005
ACM
78views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Timing driven track routing considering coupling capacitance
Abstract— As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven ro...
Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
FSTTCS
2010
Springer
15 years 4 months ago
Minimizing Busy Time in Multiple Machine Real-time Scheduling
We consider the following fundamental scheduling problem. The input consists of n jobs to be scheduled on a set of machines of bounded capacities. Each job is associated with a re...
Rohit Khandekar, Baruch Schieber, Hadas Shachnai, ...