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DAC
2011
ACM
14 years 6 months ago
Fault-tolerant 3D clock network
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...
SIGCSE
2005
ACM
163views Education» more  SIGCSE 2005»
16 years 11 days ago
Using SeSFJava in teaching introductory network courses
Networking course projects are usually described by an informal specification and a collection of test cases. Students often misunderstand the specification or oversimplify it t...
Tamer Elsharnouby, A. Udaya Shankar
LATIN
2010
Springer
15 years 12 months ago
Prize-Collecting Steiner Networks via Iterative Rounding
In this paper we design an iterative rounding approach for the classic prize-collecting Steiner forest problem and more generally the prize-collecting survivable Steiner network de...
MohammadTaghi Hajiaghayi, Arefeh A. Nasri
BMCBI
2006
126views more  BMCBI 2006»
15 years 6 months ago
A joint model of regulatory and metabolic networks
Background: Gene regulation and metabolic reactions are two primary activities of life. Although many works have been dedicated to study each system, the coupling between them is ...
Chen-Hsiang Yeang, Martin Vingron
TMC
2010
142views more  TMC 2010»
15 years 5 months ago
DGRAM: A Delay Guaranteed Routing and MAC Protocol for Wireless Sensor Networks
This paper presents an integrated MAC and routing protocol called Delay Guaranteed Routing and MAC (DGRAM) for delay sensitive wireless sensor network (WSN) applications. DGRAM is...
Shanti Chilukuri, Anirudha Sahoo