Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...
Networking course projects are usually described by an informal specification and a collection of test cases. Students often misunderstand the specification or oversimplify it t...
In this paper we design an iterative rounding approach for the classic prize-collecting Steiner forest problem and more generally the prize-collecting survivable Steiner network de...
Background: Gene regulation and metabolic reactions are two primary activities of life. Although many works have been dedicated to study each system, the coupling between them is ...
This paper presents an integrated MAC and routing protocol called Delay Guaranteed Routing and MAC (DGRAM) for delay sensitive wireless sensor network (WSN) applications. DGRAM is...