4401 search results - page 456 / 881 » Computing with Default Logic |
249
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LPNMR
2011
Springer
14 years 9 months ago
2011
Springer
This paper investigates a new approach for computing the inference of defeasible logic. The algorithm proposed can substantially reduced the theory size increase due to transformat...
146
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DAC
1998
ACM
16 years 7 months ago
1998
ACM
This paper describes the design and implementation of the NUMAchine multiprocessor. As the market for CC-NUMA multiprocessors expands, this research project provides a timely arch...
157
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DAC
1999
ACM
16 years 7 months ago
1999
ACM
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...
193
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
158
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DAC
2002
ACM
16 years 7 months ago
2002
ACM
A regular circuit structure called a River PLA and its reconfigurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with sta...