4401 search results - page 411 / 881 » Computing with Default Logic |
177
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TCAD
1998
15 years 6 months ago
1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
210
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ADHOCNETS
2010
Springer
15 years 4 months ago
2010
Springer
Event detection is a central component in numerous wireless sensor network (WSN) applications. In spite of this, the area of event description has not received enough attention. Th...
169
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DAC
2012
ACM
13 years 9 months ago
2012
ACM
Unknown values (Xs) may exist in a design due to uninitialized registers or blocks that are powered down. Due to X-pessimism in gate-level logic simulation, such Xs cannot be hand...
190
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QEST
2008
IEEE
16 years 1 months ago
2008
IEEE
We present a new version of PROBDIVINE – a parallel tool for verification of probabilistic systems against properties formulated in linear temporal logic. Unlike the previous r...
165
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KSEM
2007
Springer
16 years 28 days ago
2007
Springer
Abstract. Description logics (DLs) are a well-known family of knowledge representation (KR) languages. The notation of DLs has the style of a variable-free first order predicate l...