4401 search results - page 409 / 881 » Computing with Default Logic |
175
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ICCAD
1993
IEEE
15 years 11 months ago
1993
IEEE
Current approaches to compute and exploit the flexibility of a component in an FSM network are all at the symbolic level [23, 30, 33, 31]. Conventionally, exploitation of this ï¬...
186
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CONCUR
2009
Springer
15 years 10 months ago
2009
Springer
Abstract. We study the decidability and complexity of verification problems for timed automata over time intervals of fixed, bounded length. One of our main results is that time-bo...
170
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DSN
2004
IEEE
15 years 10 months ago
2004
IEEE
In this paper we introduce the logic asCSL, an extension of continuous stochastic logic (CSL), which provides powerful means to characterise execution paths of action- and state-l...
205
Voted
SPIN
2000
Springer
15 years 10 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
201
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WFLP
2000
Springer
15 years 10 months ago
2000
Springer
We introduce a framework for assessing the effectiveness of partial evaluators in functional logic languages. Our framework is based on properties of the rewrite system that models...