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DAC
2006
ACM
16 years 7 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
DAC
2006
ACM
16 years 7 months ago
Predicate learning and selective theory deduction for a difference logic solver
Design and verification of systems at the Register-Transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an...
Chao Wang, Aarti Gupta, Malay K. Ganai
ICML
2005
IEEE
16 years 7 months ago
Learning the structure of Markov logic networks
Markov logic networks (MLNs) combine logic and probability by attaching weights to first-order clauses, and viewing these as templates for features of Markov networks. In this pap...
Stanley Kok, Pedro Domingos
ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
16 years 8 days ago
Technology Mapping for Reliability Enhancement in Logic Synthesis
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Zhaojun Wo, Israel Koren
NMR
2004
Springer
16 years 1 days ago
On acyclic and head-cycle free nested logic programs
We define the class of head-cycle free nested logic programs, and its proper subclass of acyclic nested programs, generalising similar classes originally defined for disjunctive...
Thomas Linke, Hans Tompits, Stefan Woltran