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DAC
1997
ACM
15 years 11 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
CONCUR
1993
Springer
15 years 10 months ago
Loop Parallelization in the Polytope Model
During the course of the last decade, a mathematical model for the parallelization of FOR-loops has become increasingly popular. In this model, a (perfect) nest of r FOR-loops is r...
Christian Lengauer
ICS
1993
Tsinghua U.
15 years 10 months ago
The EM-4 Under Implicit Parallelism
: The EM-4 is a supercomputer that offers very fast inter processor communication and support for multi threading. In this paper we demonstrate that the EM-4, Together with an auto...
Lubomir Bic, Mayez A. Al-Mouhamed
AAIM
2010
Springer
165views Algorithms» more  AAIM 2010»
15 years 10 months ago
Finding Good Tours for Huge Euclidean TSP Instances by Iterative Backbone Contraction
Abstract. This paper presents an iterative, highly parallelizable approach to find good tours for very large instances of the Euclidian version of the well-known Traveling Salesma...
Christian Ernst, Changxing Dong, Gerold Jäger...
DAC
2009
ACM
15 years 10 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen