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VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
16 years 7 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
VLSID
2004
IEEE
114views VLSI» more  VLSID 2004»
16 years 7 months ago
High-Speed Optoelectronics Receivers in SiGe
This paper focuses on the investigation of integrated CMOS and Silicon/Germanium (SiGe) devices for highspeed optical receiver circuits. In this paper, we present several competit...
Amit Gupta, Steven P. Levitan, Leo Selavo, Donald ...
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VLSID
2004
IEEE
139views VLSI» more  VLSID 2004»
16 years 7 months ago
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
André Ivanov, Baosheng Wang, Josh Yang
VLSID
2003
IEEE
167views VLSI» more  VLSID 2003»
16 years 7 months ago
Timing Minimization by Statistical Timing hMetis-based Partitioning
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
Cristinel Ababei, Kia Bazargan
VLSID
2003
IEEE
78views VLSI» more  VLSID 2003»
16 years 7 months ago
Interface Design Techniques for Single-Chip Systems
This paper quantifies the performance of typical functional unit interface designs in single-chip systems. We introduce a specific equation to guide the design of optimal module i...
Robert H. Bell Jr., Lizy Kurian John
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