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DAC
1999
ACM
16 years 8 months ago
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
Chung-Ping Chen, Noel Menezes
DAC
2002
ACM
16 years 8 months ago
A solenoidal basis method for efficient inductance extraction
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
Hemant Mahawar, Vivek Sarin, Weiping Shi
DAC
2003
ACM
16 years 8 months ago
State-based power analysis for systems-on-chip
Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for ...
Reinaldo A. Bergamaschi, Yunjian Jiang
DAC
2003
ACM
16 years 8 months ago
Support vector machines for analog circuit performance representation
The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parame...
Fernando De Bernardinis, Michael I. Jordan, Albert...
DAC
2003
ACM
16 years 8 months ago
Random walks in a supply network
This paper presents a power grid analyzer based on a random walk technique. A linear-time algorithm is first demonstrated for DC analysis, and is then extended to perform transien...
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
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