Sciweavers

15485 search results - page 2650 / 3097
» Computing Optimal Subsets
Sort
View
DAC
2006
ACM
16 years 7 months ago
Power-centric design of high-speed I/Os
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojan...
DAC
2006
ACM
16 years 7 months ago
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
DAC
2006
ACM
16 years 7 months ago
Efficient SAT-based Boolean matching for FPGA technology mapping
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
Sean Safarpour, Andreas G. Veneris, Gregg Baeckler...
DAC
2006
ACM
16 years 7 months ago
Gate sizing: finFETs vs 32nm bulk MOSFETs
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
Brian Swahn, Soha Hassoun
MICCAI
2007
Springer
16 years 7 months ago
Effects of Registration Regularization and Atlas Sharpness on Segmentation Accuracy
In this paper, we propose a unified framework for computing atlases from manually labeled data at various degrees of "sharpness" and the joint registration-segmentation o...
B. T. Thomas Yeo, Mert R. Sabuncu, Rahul Desikan, ...
« Prev « First page 2650 / 3097 Last » Next »