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166
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HPCA
2008
IEEE
16 years 7 months ago
2008
IEEE
A conceptually appealing approach to supporting a broad range of workloads is a system comprising many small cores that can be fused, on demand, into larger cores. We demonstrate ...
209
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HPCA
2007
IEEE
16 years 7 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
144
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes p...
154
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HPCA
2003
IEEE
16 years 7 months ago
2003
IEEE
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...
188
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HPCA
2003
IEEE
16 years 7 months ago
2003
IEEE
Scalability of applications on distributed sharedmemory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism y...