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HPCA
2009
IEEE
16 years 7 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
VLSID
2007
IEEE
149views VLSI» more  VLSID 2007»
16 years 6 months ago
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes
Title of thesis: EFFICIENT AND ACCURATE STATISTICAL TIMING ANALYSIS FOR NON-LINEAR NON-GAUSSIAN VARIABILITY WITH INCREMENTAL ATTRIBUTES Ashish Dobhal, Master of Science, 2006 Thes...
Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
16 years 6 months ago
A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity
With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Eventtransients (SET), is a ...
Mohammad Gh. Mohammad, Laila Terkawi, Muna Albasma...
VLSID
2004
IEEE
125views VLSI» more  VLSID 2004»
16 years 6 months ago
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software
The increasing software content of battery-powered embedded systems has fueled much interest in techniques for developing energyefficient embedded software. Source code transforma...
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj...
VLSID
2002
IEEE
99views VLSI» more  VLSID 2002»
16 years 6 months ago
Input Space Adaptive Embedded Software Synthesis
This paper presents a novel technique, called input space adaptive software synthesis, for the energy and performance optimization of embedded software. The proposed technique is ...
Weidong Wang, Anand Raghunathan, Ganesh Lakshminar...
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