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VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
15 years 10 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
AI50
2006
15 years 10 months ago
A Human-Like Robot Torso ZAR5 with Fluidic Muscles: Toward a Common Platform for Embodied AI
"Without embodiment artificial intelligence is nothing." Algorithms in the field of artificial intelligence are mostly tested on a computer instead of testing on a real p...
Ivo Boblan, Rudolf Bannasch, Andreas Schulz, Hartm...
ATS
2004
IEEE
93views Hardware» more  ATS 2004»
15 years 10 months ago
Hybrid BIST Test Scheduling Based on Defect Probabilities
1 This paper describes a heuristic for system-on-chip test scheduling in an abort-on-fail context, where the test is terminated as soon as a defect is detected. We consider an hybr...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
DFT
2004
IEEE
90views VLSI» more  DFT 2004»
15 years 10 months ago
An XOR Based Reed-Solomon Algorithm for Advanced RAID Systems
In this paper, a simple codec algorithm based on Reed-Solomon (RS) codes is proposed for erasure correcting in RAID (Redundant Array of Independent Disks) level 6 systems. Unlike ...
Ping-Hsun Hsieh, Ing-Yi Chen, Yu-Ting Lin, Sy-Yen ...
FCCM
2004
IEEE
141views VLSI» more  FCCM 2004»
15 years 10 months ago
Deep Packet Filter with Dedicated Logic and Read Only Memories
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...
Young H. Cho, William H. Mangione-Smith
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