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SBACPAD
2006
IEEE
102views Hardware» more  SBACPAD 2006»
16 years 23 days ago
Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck
SBACPAD
2006
IEEE
148views Hardware» more  SBACPAD 2006»
16 years 23 days ago
Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact Inference
We present a scalable parallel implementation for converting a Bayesian network to a junction tree, which can then be used for a complete parallel implementation for exact inferen...
Vasanth Krishna Namasivayam, Animesh Pathak, Vikto...
VLSID
2006
IEEE
112views VLSI» more  VLSID 2006»
16 years 23 days ago
Handling Constraints in Multi-Objective GA for Embedded System Design
Design space exploration is central to embedded system design. Typically this is a multi-objective search problem, where performance, power, area etc. are the different optimizati...
Biman Chakraborty, Ting Chen, Tulika Mitra, Abhik ...
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
16 years 23 days ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
APCSAC
2005
IEEE
16 years 12 days ago
Energy-Effective Instruction Fetch Unit for Wide Issue Processors
Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such ...
Juan L. Aragón, Alexander V. Veidenbaum
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