Sciweavers

11061 search results - page 1813 / 2213
» Computer Architecture
Sort
View
SBACPAD
2007
IEEE
85views Hardware» more  SBACPAD 2007»
16 years 1 months ago
Exigency-based real-time scheduling policy to provide absolute QoS for web services
— Telemedicine, distance learning and e-commerce applications impose time constraints directly related to the efficacy of their operations. In order to offer reliability levels ...
Lucas S. Casagrande, Rodrigo Fernandes de Mello, R...
SBACPAD
2007
IEEE
143views Hardware» more  SBACPAD 2007»
16 years 1 months ago
A Code Compression Method to Cope with Security Hardware Overheads
Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security ...
Eduardo Wanderley Netto, Romain Vaslin, Guy Gognia...
FPL
2007
Springer
105views Hardware» more  FPL 2007»
16 years 28 days ago
Time Predictable CPU and DMA Shared Memory Access
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
Christof Pitter, Martin Schoeberl
APCSAC
2006
IEEE
16 years 25 days ago
Using Branch Prediction Information for Near-Optimal I-Cache Leakage
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the perform...
Sung Woo Chung, Kevin Skadron
ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
16 years 24 days ago
Improving Cost, Performance, and Security of Memory Encryption and Authentication
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encrypt...
Chenyu Yan, Daniel Englender, Milos Prvulovic, Bri...
« Prev « First page 1813 / 2213 Last » Next »